• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A driving circuit (6) having a first set of transformers (20) connected to a pulse amplifier module 12 and a second set of transformers (40) connected to a plurality of power component groups (70) to semiconductors, each group (70) comprising one or more power devices. The first set of transformers (20) comprises at least one primary transformer adapted to receive in a primary winding (22) a current pulse emitted by a current pulse generating module, the current pulse being reflected back to a winding secondary (24). The second set of transformers (40) includes a plurality of secondary transformers, each secondary transformer being adapted to receive the current pulse in a primary winding (42) thereof, the current pulse being reflected to a secondary winding (44) coupled to a pulse receiving module (50). The first and second sets of transformers (20, 21) reduce parasitic coupling between the pulse receiving module (50) and the control module (10).
    公开号:FR3036013A1
    申请号:FR1554105
    申请日:2015-05-07
    公开日:2016-11-11
    发明作者:Christopher Joseph Lee；Luke Anthony Solomon；Alfred Permuy
    申请人:GE Energy Power Conversion Technology Ltd；
    IPC主号:
    专利说明:

    [0001] The present invention relates to an electronic power system that employs a transformer enable system for galvanically isolated active power devices. A number of different current conversion systems convert one current from one form to another. For example, a multi-level UPS is an electronic power device structured to produce an AC signal (AC) from a DC input voltage (c.c.). These current conversion systems are used in all kinds of applications such as motor speed controllers. Isolation, and independent control in current conversion systems, is provided by gate driver circuits. The gate drivers convert logic level control signals into appropriate voltages for switching one or more power devices of a group of power semiconductor components. In most cases, these circuits provide galvanic isolation to prevent the exposure of logic signals to potentially dangerous high voltages in the power circuit. Many conventional techniques allow isolation and control functions using gate drivers. For example, a first technique directly transfers a voltage across a barrier, via a transformer, while maintaining the galvanic isolation. When using a transformer, a common voltage across the secondary is produced when a voltage level change occurs in the power semiconductor component group. This common voltage causes parasitic currents to flow in the control circuit, which may cause a failure or inadvertent operation. Another technique uses fiber optic transmission to create the conduction / non-conduction digital signal while routing the current separately with an isolated power source. However, these prior art techniques are expensive and lack accurate timing for controlling serial power-coupled devices (eg, switches). In view of the problem discussed above, systems and methods are needed which allow accurate timing for controlling series-connected power devices to operate circuits in high voltage environments with a high rate of change of power. voltage with respect to time. The present invention includes a driver circuit for energizing an electrical system. The driver circuit comprises a first set of transformers connected to a pulse amplifier module and a second set of transformers connected to a plurality of power semiconductor component groups, each group containing one or more devices. of commutation. The first and second sets of transformers provide galvanic isolation and reduce parasitic coupling between the control module and the pulse receiving module. To each additional transformer added in series between the first primary winding and the last secondary winding, additional capacity is added in the electronic system. As a result, the collective capacitance decreases between the first primary winding and the last secondary winding. The first set of transformers comprises at least one primary transformer adapted to receive, in a primary winding, a current pulse supplied by a current pulse generator controlled by a control module. In addition, the current pulse is reflected to a secondary winding. The second set of transformers comprises a plurality of secondary transformers, each secondary transformer being adapted to receive the current pulse in a primary winding. In addition, the current pulse is reflected to a secondary winding coupled to a pulse receiving module.
    [0002] Other aspects and advantages of the invention, as well as the structure and operation of various embodiments of the invention are described in detail hereinafter with reference to the accompanying drawings. It will be appreciated that the invention is not limited to the specific embodiments described herein. These embodiments are presented here for illustrative purposes only. Additional embodiments will be apparent to those skilled in the art (s) based on the principles explained herein. The invention will be better understood from the detailed study of some embodiments taken as non-limiting examples and illustrated by the appended drawings in which: FIG. 1 is a schematic illustration of an electronic system in a form embodiment of the present invention; FIG. 2 is a schematic illustration of logic level signals determining four types of current pulses in the gate driver of the electronic system according to FIG. 1; Figure 3 is a schematic illustration of an electronic system according to a second embodiment of the present invention; and FIG. 4 is a schematic illustration of an electronic system according to a third embodiment. FIG. 1 is an illustration of an exemplary electronic system 2 having a driving circuit 6 connected to a plurality of semiconductor component groups 70. The driving circuit 6 comprises a control module 10, a amplification module 12 of current pulses, a first set of transformers 20 and a second set of transformers 40.
    [0003] The control module 10 of the gate driver 6 comprises one or more devices capable of generating logic level control signals in accordance with a particular programming. In one embodiment, the control module 10 is programmed to produce a number of logic level signals to shape a current pulse to be applied to the current pulse amplification module 12. As described below, the current pulse serves to produce the voltage signals exciting power devices of each group of semiconductor components 70.
    [0004] The power devices are semiconductors serving as a switch or rectifier capable of selectively switching between a nonconductive (blocking) state and a conducting state (passing) under the action of an input control signal, and This will include, for example, thyristors, bipolar junction transistors (TBJ), insulated gate bipolar transistors (TBGI), or metal oxide-semiconductor field effect transistors (MOSFETs). The power devices can be classified into two categories depending on the excitation requirements, namely, active semiconductor power devices without gate oxide isolation and isolation active power semiconductor devices. by gate oxide. The control module 10 communicates with the current pulse amplification module 12 via one or more logic signals 11. The current pulse amplification module 12 delivers current pulses in function of the logic signals 11 delivered by the control module 10. As illustrated in FIG. 2, the logic signals 11 may include any number of current pulses passing through three logic states (e.g., High, Low). , Neutral). The current pulse may, for example, comprise (i) a blocking pulse that switches each semiconductor of each group of semiconductor components 70 from a conductive (conducting) state to a non-conductive state ( blocking). The current pulse may also include (ii) a deblocking pulse that switches each semiconductor of each group of semiconductor components 70 from a nonconductive (blocking) state to a conductive (passing) state, and (iii) a blocking refresh pulse, which maintains in each non-conductive state each semiconductor of each group of semiconductor components 70 when the power devices are already in a blocking state. In addition, (iv) a deblocking refresh pulse maintains in conductive state each semiconductor component of each group of semiconductor components 70 when the power devices are already in an on state. As shown in FIG. 2, the control module 10 applies to the current pulse amplification module 12 two types (blocking and unblocking pulses) of logic signals 11 each representing a type of current pulse. For example, a logic signal A goes through three logic states (eg, High, Low, Neutral) and another logic signal 11 (logic signal B) only passes through two logic states (e.g. Low). In the electronic system 2 of FIG. 2, the logic signal B produces a zero volt state in the first set of transformers 20 when the logic signal A is in the neutral state. This arrangement ensures that the second set of transformers 40 does not output a switch gage load from the semiconductor component groups 70 after the current pulse has been emitted. The current pulse produced by the logic signal A and supplied to the current pulse amplification module 12 is applied to windings of the set of transformers 20, in particular to primary windings 22. In response, a 15 current pulse is reflected to the secondary windings 24 of the first set of transformers 20. In other words, the application of the current pulse produced by the logic signal A to the primary windings 22 results in M substantially identical reflected current pulses of which the The amplitude is modified by the secondary windings 24 according to a transformation ratio in the secondary windings 24. One advantage of such use of the first set of transformers 20 is that it produces the M reflected current pulses of a synchronously in the secondary windings 24 while simultaneously providing galvanic isolation between the com modulus Means 10 and the logic signal for the current pulse amplification module 12 and the higher (potentially dangerous) voltage of the active power semiconductor component groups 70.
    [0005] The first set of transformers 20 comprises primary windings 22 coupled to secondary windings 24. In some embodiments, the primary windings 22 are identical to each other and the secondary windings 24 are identical to each other ( for example uses the same magnetic core, the same transformation ratio and the same leakage inductance). However, in other embodiments, the primary windings 22 and the secondary windings 24 may differ from each other. In high common-mode environments, parasitic capacitive coupling between the semiconductor component groups 70 and the driving circuit 6 may adversely affect the performance of the system 2 by causing a failure or inadvertent operation of circuit components. In particular, a high speed of voltage variation with respect to the time (dv / dt) of the semiconductor power components causes the appearance of a large variation of the voltage level on the primary windings. (eg the primary windings 42 of the second set of transformers 40) with respect to a control voltage reference node. This variation in the voltage level causes a common mode current flow from the power devices of the semiconductor component groups 70 to the current pulse amplification module 12 and the control module 10. The current For example, common mode switching may interrupt the typical switching of low voltage power devices 25 in the pulse amplifier module 12 and cause untimely operation of these low voltage power devices. In addition, inadvertent operation may cause power devices to fail in the semiconductor component groups 70.
    [0006] Furthermore, common-mode galvanic isolation does not exist in system 2. Common-mode voltage can cause the flow of common-mode current in low voltage electronic components and ground loops. measurement systems with multiple grounding points. The common mode voltage that exceeds a maximum overvoltage rating of the semiconductor component group switches 70 may damage components of the driver circuit 6. The presence of the first set of transformers 20 reduces the stresses due to to the dv / dt ratio of the control module 10 10, which occurs when the power devices of the semiconductor component groups 70 switch under the effect of the increase of the common mode impedance in the system 2. By For example, the first set of transformers 20 reduces the capacitance between the control module 10 and the power devices of the semiconductor component groups 70. Including a series transformer winding increases the capacitance of the circuit board. attack 6 by the capacitance in series and thus reduces the overall capacitive coupling between the first primary winding and the last secondary winding.
    [0007] In other embodiments, illustrated in FIGS. 3 and 4, the first set of transformers 20 may comprise up to N primary windings 22 (denoted by 1 to N) coupled to N secondary windings 24 (designated 1 to NOT). Each of the M primary windings 22 is identical to the other primary windings 22. Likewise, each of the M secondary windings 24 is identical to other secondary windings 24 (i.e. the same magnetic core is used, the same ratio of transformation and the same leakage inductance). Each primary winding 22 (1 to N) of the second set of transformers 40 may be wired in parallel to allocate the current. In parallel configurations, the logic signal supplied to the current pulse amplifier module 12 is applied to the primary winding 22 of a first transformer 20-1 of the first set of transformers 20. According to another Alternatively, primary windings 22 (15-N) may be connected in series with each other so that all transformers of the first set of transformers 20 have the same current. In series arrangements, the logic signal 11 supplied to the current pulse amplification module 12 is applied to each primary winding 22 of the first set of transformers 20 so that each primary winding 22 receives the same signal (FIG. that is to say, the same current pulse) delivered by the current pulse amplification module 12. In some embodiments, a loop 30 connects the first set of transformers 20 and the second set of transformers 40. In particular, loop 30 connects secondary windings 24 of the first set of transformers 20 to a potential in system 2. Due to the connection of the first set of transformers 20 to a potential 20 in the system 2, the capacitive coupling is reduced. In other embodiments, the loop 30 is connected to a potential located at a midpoint of the system 2. An exemplary configuration, illustrated in Figure 1, shows the loop 30 connected to a DC circuit 80 of the system. 2.
    [0008] In particular, the loop 30 creates additional current feedback paths to the source of the common mode voltage and allows the common mode current to be directed from the power electronics (eg the gate circuit 2). The loop 30 provides a low impedance return path from the semiconductor component group 70 to the reference node source of the voltage level change. The connection of the driving circuit 6 to a voltage potential creates a higher parasitic impedance on the return from the current pulse amplifier module 12 to the loop 30 rather than via the same connection in the primary windings. 42, which circulates current over a low impedance path that avoids the electronic components in the control module 10. If there are multiple transformers in the first set of transformers 20, as shown in FIGS. at each of the transformers 20-1 to 20-N of the first set of transformers is associated a loop 30 (denoted by 1 to N). Each of the loops 30-1 to 30-N is connected to a potential voltage of the system 2. In some embodiments with multiple transformers, each loop 30 may be connected to the same potential in the system 2. For example, the loops 30-1 to 30-N may be connected to the midpoint of a DC circuit 80. In another example, illustrated in Figure 3, the first loop 30-1, the second loop 30-2 and the Nth loop 30-N can each be connected to one of the semiconductor component groups 70 (eg 70-2 in the illustration). In some embodiments with multiple transformers, one or more loops 30 may be connected to different potentials in the system 2. For example, as shown in FIG. 4, loops 30-1 and 30-N are 25 connected to the midpoint of the capacitor DC circuit 80. However, the loop 30-2 is connected to the second group of semiconductor components 70-2. The driver circuit 6 also includes the second set of transformers 40. The second set of transformers 40 receives pulses from the current pulse amplifier module 12 through the first set of transformers 20. Second set of transformers 40 comprises M primary windings 42 (denoted by 1 to M) coupled in the manner described above to M secondary windings 44 (denoted by 1 to M). The primary windings 42-1 to 42-M of the second set of transformers 40 are connected in series so that all the transformers of the second set of transformers 40 have the same signal (current pulse). Thus, current pulses received by the primary windings 42 of the second set of transformers 40 create substantially identical reflected reflective current pulses with the ratio of the number of turns between the secondary and the primary windings in the secondary windings 44. one such use of the second set of transformers 40 is that it generates the M reflected current pulses in a synchronized manner in the secondary windings 44. This occurs while simultaneously adding a capacitance in series between the control module 10 and the logic signal in the current pulse amplification module 12 and the higher (potentially dangerous) voltage of the semiconductor component groups 70. Thus, the first set of transformers 20 and the second set of transformers 40 25 collectively increase the common mode impedance between the control module 10 and each of the pulse receiving modules 50-1 to 50-M. Each of the secondary windings 44-1 to 44-M of the second set of transformers 40 connects to M pulse receiving modules (designated 1 to M). Each pulse receiving module 50 is coupled to one or more switch arrays of one of the semiconductor component groups 70. Each pulse receiving module 50 transmits and locks the current pulse. Receptor suitable for controlling the switches of the associated semiconductor component group 70. More particularly, each pulse receiving module 50 performs two main functions on the received current pulses in order to establish a voltage (e.g. a gate-emitter voltage) for making switches of semiconductor component groups 70 either conductive (on state) or non-conductive (blocking state). First, the pulse receiving module 50 adjusts and settles on a gate-emitter voltage in an on state for a positive current pulse. Likewise, the pulse receiving module 50 adjusts and settles on a gate-emitter voltage in a blocking state for a negative current pulse. Then, the pulse receiving module 50 remains at the gate-emitter voltage in the on state or blocking state after the current pulse has ended so that the switches of a group of components of active semiconductor power 70 can remain respectively in the on state or in the blocking state. This prevents a flux resetting action of the second set of transformers 40 from inadvertently disturbing the proper gate-emitter voltages in the on state and the blocking state. The components of the electronic system 2 can be made more resistant to electromagnetic noise (EMI) to be better protected against the presence of electromagnetic waves in the atmosphere. Such EMI-resistant components 3036013 13 can prevent detected signals from propagating to the connected circuits of the driver 6.
    [0009] 3036013 14 List of markers Figure 1 2 - Electronic system 5 6 - Driver 10 - Control module 11 - Logic signal 12 - Amplifier module 20 - Transformer assembly 10 22 - Primary windings 24 - Secondary windings 30 - Loop 40 - Transformer Assembly 42 (1 to M) - Primary Winding 15 44 (1 to M) - Secondary Winding 50 (1 to M) - Receiving Module 70 (1 to M) - Solid State Component Group 80 - DC circuit 20 Figure 2 10 - Control module 11 - Logic signal 12 - Amplification module 22 - Primary windings 25 Figure 3 2 - Electronic system 6 - Drive circuit 10 - Control module 30 11 - Logic signal 12 - Amplifier module 3036013 15 20 (1 to N) - Transformer assembly 22 - Primary windings 24 (1 to N) - Secondary windings 30 (1 to N) - Loop 5 40 - Transformer assembly 42 (1 to M) - Primary winding 44 (1 to M) - Secondary winding 50 (1 to M) - Receiver module 70 (1 to M) - Solid state component group 10 80 - Direct current circuit Figure 4 2 - Electronic system 6 - Driver circuit 15 10 - Control module 11 - Logic signal 12 - Amplifier module 20 - Transformer assembly 22 - Primary windings 20 24 - Secondary windings 30 - Loop 40 - Transformer assembly 42 (1 to M) - Primary winding 44 (1 to M) - Secondary winding 25 50 (1 to M) - Receive module 70 (1 to M) - Solid state component group 80 - DC circuit
    权利要求:
    Claims (20)
    [0001]
    REVENDICATIONS1. A driving circuit (6) for controlling a plurality of semiconductor power devices, comprising: a first set of transformers (20) comprising at least one primary transformer (20-1 ... 20-N) configured for receiving in a primary winding (22) a current pulse emitted by a current pulse generating module, the current pulse being reflected to a secondary winding (24) of the primary transformer (20-1 ... 20- NOT) ; and a second set of transformers (40) including a plurality of secondary transformers (40-1 ... 40-N), each secondary transformer (40-1 ... 40-N) being adapted to receive the current pulse in a primary winding (42) thereof, the current pulse being reflected to a secondary winding (44) of the secondary transformer (40-1 ... 40-N) coupled to a receiving module (50) d pulses, the first and second sets of transformers (20, 40) reducing parasitic coupling between the control module (10) and the pulse receiving module (50).
    [0002]
    The driving circuit (6) according to claim 1, wherein the first set of transformers (20) comprises a first primary transformer (20-1) connectable to the pulse generating module and a second primary transformer (20). 2) connectable to the second set of transformers (40), the first and second transformers being connected to each other.
    [0003]
    The driving circuit (6) of claim 2, further comprising a third primary transformer (20-3) mounted between the first primary transformer (20-1) and the second primary transformer (20-2).
    [0004]
    The driving circuit (6) of claim 1, wherein the first set of transformers (20) further comprises a voltage loop (30) connectable to a reference node of the electronic system (2).
    [0005]
    The driving circuit (6) according to claim 4, wherein the voltage loop (30) is connected to a midpoint of multiple voltage references in series. 10
    [0006]
    The driving circuit (6) according to claim 2, wherein the first primary transformer (20-1) comprises a first voltage loop (30-1) connectable to a first reference node of the electronic system (2) and the second primary transformer (20-2) comprises a second voltage loop (30-2) connectable to a second reference node of the electronic system (2).
    [0007]
    The driver circuit (6) of claim 6, wherein the first reference node is at the same location as the second reference node. 20
    [0008]
    The driving circuit (6) according to claim 1, wherein the primary transformers (20-1 ... 20-N) of the first set of transformers (20) or the secondary transformers (40-1 ... 40N). ) of the second set of transformers (40) are made using toroids. 25
    [0009]
    An electronic system (2) comprising: a gate driver (6) comprising: a first set of transformers (20) having at least one primary transformer (20-1 ... 20-N) adapted to receive in a primary winding (22) a current pulse emitted by a current pulse generating module, the current pulse being reflected to a secondary winding (24) of the primary transformer (20-1 ... 20 -NOT) ; and a second set of transformers (40) having a plurality of secondary transformers (40-1 ... 40-N), each secondary transformer (40-1 ... 40-N) being adapted to receive the pulse of current in a primary winding (42) thereof, the current pulse being reflected to a secondary winding (44) of the secondary transformer (40-1 ... 40-N) coupled to a receiving module (50) pulses, the first and second sets of transformers (20, 40) providing reduced coupling between the control module (10) and the pulse receiving module (50); and a plurality of serially active solid-state power component groups, each group of solid-state active power components comprising one or more semiconductor devices and connectable to the receiving modules corresponding pulses (50).
    [0010]
    The system (2) of claim 9, wherein the first set of transformers (20) comprises a first primary transformer (20-1) connectable to the pulse generating module and a second primary transformer (20-2). connectable to the second set of transformers (40), the first and second transformers being connected to each other.
    [0011]
    The system (2) of claim 10, further comprising a third primary transformer (20-3) mounted between the first primary transformer (20-1) and the second primary transformer (20-2).
    [0012]
    The system (2) of claim 9, wherein the first set of transformers (20) further comprises a voltage loop (30) connectable to a reference node of the electronic system (2). 3036013 19
    [0013]
    The system (2) of claim 12, wherein the voltage loop (30) is connected to a midpoint of multiple voltage references in series.
    [0014]
    The system (2) of claim 10, wherein the first primary transformer (20-1) comprises a first voltage loop (30-1) connectable to a first reference node of the electronic system (2) and the second primary transformer (20-2) comprises a second voltage loop (30-2) connectable to a second reference node of the electronic system (2).
    [0015]
    The system (2) of claim 14, wherein the first reference node is at the same location as the second reference node.
    [0016]
    The system (2) of claim 9, wherein the primary transformers (20-1 ... 20-N) of the first set of transformers (20) or the secondary transformers (40-1 ... 40N) of the second set of transformers (40) are made using toroids.
    [0017]
    A method for controlling an electronic system (2), comprising: receiving, by a first set of transformers (20) comprising at least one primary transformer (20-1 ... 20N), a current pulse in a primary winding (22), emitted by a current pulse generator 25 controlled by a control module (10); communicating the current pulse to a secondary winding (24) of the primary transformer (20-1 ... 20-N); receiving, by a second set of transformers (40) having a plurality of secondary transformers (40-1 ... 40-N), 3036013 of the current pulse in a primary winding (42-1 ... 42M) of each secondary transformer (40-1 ... 40-N); and communicating the current pulse to a secondary winding (44-1 ... 44-N) of each of the secondary transformers (40-1 ... 40-M), the secondary winding (44-1 44-M) of each of the secondary transformers (40-1 ... 40-N) being adapted to be coupled to a pulse receiving module (50), the first and second sets of transformers (20, 40) strongly limiting parasitic coupling 10 between the control module (10) and the pulse receiving module (50).
    [0018]
    The method of claim 17, wherein the first set of transformers (20) comprises a first primary transformer (20-1) connectable to the pulse generator module and a second primary transformer (20-2) connectable to the second a set of transformers (40), the first and second primary transformers (20-1, 20-2) being connected to each other.
    [0019]
    The method of claim 17, wherein the first set of transformers (20) further comprises a voltage loop (30) connectable to a reference node of the electronic system (2).
    [0020]
    The method of claim 18, wherein the first primary transformer (20-1) comprises a first voltage loop (30-1) connectable to a first reference node of the electronic system (2) and the second primary transformer ( 20-2) comprises a second voltage loop (30-2) connectable to a second reference node of the electronic system (2).
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    法律状态:
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    2016-11-11| PLSC| Publication of the preliminary search report|Effective date: 20161111 |
    2017-05-25| PLFP| Fee payment|Year of fee payment: 3 |
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    2022-02-11| ST| Notification of lapse|Effective date: 20220105 |
    优先权:
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    FR1554105A|FR3036013B1|2015-05-07|2015-05-07|GATE ATTACK CIRCUIT FOR REDUCING PARASITE COUPLING|
    FR1554105|2015-05-07|FR1554105A| FR3036013B1|2015-05-07|2015-05-07|GATE ATTACK CIRCUIT FOR REDUCING PARASITE COUPLING|
    CA2928189A| CA2928189A1|2015-05-07|2016-04-28|Gate drive circuit to reduce parasitic coupling|
    DE102016108187.6A| DE102016108187A1|2015-05-07|2016-05-03|Gate drive circuit for reducing parasitic coupling|
    GB1607876.8A| GB2540020B|2015-05-07|2016-05-05|Gate drive circuit to reduce parasitic coupling|
    US15/147,920| US9887697B2|2015-05-07|2016-05-06|Gate drive circuit to reduce parasitic coupling|
    CN201610295395.1A| CN106130322B|2015-05-07|2016-05-06|Gate driving circuit for reducing parasitic coupling|
    BR102016010404A| BR102016010404A2|2015-05-07|2016-05-09|drive circuit, electrical system and method for driving an electrical system|
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